Different types of semiconductor components are tested following the fabrication process. Test systems have been developed for handling the components, and for applying test signals to the integrated circuits, and other electrical elements, contained on the components. For example, discrete semiconductor components, such as bare dice and chip scale packages, are tested at the die level using carriers designed to temporarily package one or more components. Semiconductor or wafers containing multiple dice or multiple chip scale packages, are tested using wafer level systems, such as wafer probers. Other electronic assemblies containing semiconductor dice or packages, such as circuit boards, and field emission displays, are also tested following fabrication.
The components include terminal contacts which provide electrical connection points for applying the test signals. For example, bare dice and semiconductor wafers typically include bond pads which function as terminal contacts. Chip scale packages typically include solder balls, which function as terminal contacts. Electronic assemblies, such as circuit boards and field emission displays, can include test pads, which function as terminal contacts.
The test systems include an interconnect that makes the temporary electrical connections with the terminal contacts on the components. Depending on the system, the interconnect can be die sized, or wafer sized. U.S. Pat. No. 5,686,317 entitled "Method For Forming An Interconnect Having A Penetration Limited Contact Structure For Establishing A Temporary Electrical Connection With A Semiconductor Die", describes a die level interconnect configured for use with a carrier. U.S. Pat. No. 5,869,974 entitled "Micromachined Probe Card Having Compliant Contact Members For Testing Semiconductor Wafers", describes a wafer level interconnect configured for use with a wafer prober.
One material that can be used to fabricate interconnects is silicon. Silicon is used as a substrate material and also to form contacts for the interconnect. With silicon, a coefficient of thermal expansion (CTE) of the interconnect matches the CTE of the component. This minimizes thermal stresses during test procedures, such as burn-in, which are conducted at elevated temperatures.
One aspect of silicon is that it is a relatively rigid material that does not easily flex to accommodate differences in the planarity of the contacts on the components. Accordingly, silicon interconnects require relatively large biasing forces to permit the interconnect contacts to engage the component contacts. Often times the component, rather than the interconnect, will flex under the large forces applied during test procedures. However, in order to minimize the possibility of damage to components, it is preferable that the components not be overloaded, or stressed, during a test procedure.
Sometimes the interconnect contacts, are designed to flex to accommodate variations in the planarity, or z-direction location, of the terminal contacts on the components. However, this can make the interconnect more complicated and less reliable, and may require relatively complicated fabrication processes. The present invention is directed to an interconnect which is thinned to provide a flexible structure for engaging semiconductor components.